Integrated circuit devices such as microprocessors, memories and other peripheral circuits typically operate in a synchronized fashion at very high speeds. For example, such devices may operate in synchronization with an external clock signal using an internal clock signal which is delayed for a predetermined length of time with respect to the external clock signal. The performance of such devices may be subject to degradation at the high clock frequencies associated with high speed operations. For example, the length of time used for outputting data after the external clock signal is applied, sometimes referred to as the output data access time tAC, may be lengthened. Thus, such a device often includes one or more circuits for generating clock signals synchronized to a reference clock signal. One example of a circuit for synchronizing an external clock and an internal clock is a delay locked loop (DLL) which may reduce deterioration of the operational performance of the integrated circuit device at high frequencies. The DLL is also widely used for a clock recovery systems, time-to-digital conversion circuits, and high speed serial links.
A typically DLL circuit generates a delayed clock signal from a reference clock signal, with the delayed clock signal typically being used as a reference signal for operation of devices. A typically DLL circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal. A DLL may be implemented as an analog DLL, a digital DLL, or a hybrid DLL may be used. The analog DLL typically has good jitter characteristics but may be locked into an incorrect (false) state in which the internal clock signal is delayed by one or even more periods with respect to an external clock signal. False locking is generally undesirable due to potentially increased noise susceptibility as well as jitter accumulation.
FIG. 1 illustrates a prior art analog DLL. As shown in FIG. 1, the prior art analog DLL includes a delay line 11 including a plurality of unit delays d1 through dn which are connected in series. A phase detector 13 receives an input clock signal CLKIN and an output clock signal CLKOUT of the delay line 11 to detect the difference in phase between them. A charge pump circuit 15 generates a control voltage to vary the delay time of the unit delays d1 through dn in response to output signals FWD and BCK from the phase detector 13. In the illustrated DLL, the input clock signal CLKIN may be an external clock signal and the output clock signal CLKOUT may be an internal clock signal.
The phase detector 13 may be a reset-set (RS) type phase detector or a three-state phase frequency detector (PFD). Operational timing diagrams of an RS type phase detector are illustrated in FIGS. 2a and 2b. Operational timing diagrams of the three-state PFD are illustrated in FIGS. 3a and 3b. FIGS. 2a and 3a show the timing for the case in which the total delay tTOTAL of the delay line 11 is less than the period T of the input clock signal CLKIN. In other words, for tTOTAL=.DELTA.. FIGS. 2B and 3B illustrate timing for the case in which the total delay tTOTAL of the delay line 11 is more than the period T of the input clock signal CLKIN. In other words, for tTOTAL=.DELTA.+T.
In the illustrated analog DLL using the RS type phase detector or the three-state PFD as the phase detector 13, when tTOTAL=.DELTA., the output signal FWD controls the charge pump circuit 15 to increase the delay time of the unit delays d1 through dn, so that the analog DLL may be locked to provide a delay time of tTOTAL=T. However, when tTOTAL=.DELTA.+T, the output signals BCK and FWD are controlled in the same manner as in the case when tTOTAL=.DELTA.. As a result, the analog DLL may be maintained in a false state, i.e., locked to a delay in which tTOTAL=2T.
In other words, the RS type phase detector or the three-state PFD provides the same output signals BCK and FWD for under conditions when tTOTAL=.DELTA.+mT, where m=0, 1, 2, . . . , and, thus, when tTOTAL=.DELTA.+mT, where m=1, 2, . . . , the analog DLL is in a false state, i.e., locked to a delay condition in which tTOTAL=nT, where n=2, 3, 4, . . . , In many cases, the unit delays d1 through dn are provided with a limited range of possible delays, therefore, a false state is most likely locked in to a condition where tTOTAL=2T.
It is known to take certain steps to limit the potential for false locking. For example, the delay time of the unit delays d1 through dn can be initialized to a minimum or maximum value such that the analog DLL may be able to recognize whether the delay time of the unit delays d1 through dn is to be increased or reduced to suppress false locking. However, additional circuits or an increase in locking time are typically required to implement these approaches.